1/9 may 2002 STD3NC50 STD3NC50-1 n-channel 500v - 2.2 w - 3.2a dpak / ipak powermesh?ii mosfet n typical r ds (on) = 2.2 w n extremely high dv/dt capability n 100% avalanche tested n new high voltage benchmark n gate charge minimized description the powermesh ? ii is the evolution of the first generation of mesh overlay ?. the layout re- finements introduced greatly improve the ron*area figure of merit while keeping the device at the lead- ing edge for what concerns swithing speed, gate charge and ruggedness. applications n high current, high speed switching n swith mode power supplies (smps) n dc-ac converters for welding equipment and uninterruptible power supplies and motor drivers absolute maximum ratings (?)pulse width limited by safe operating area (1)i sd 3.2a, di/dt 100a/s, v dd v (br)dss , t j t jmax. type v dss r ds(on) i d STD3NC50 STD3NC50-1 500 v 500 v < 2.7 w < 2.7 w 3.2 a 3.2 a symbol parameter value unit v ds drain-source voltage (v gs = 0) 500 v v dgr drain-gate voltage (r gs = 20 k w ) 500 v v gs gate- source voltage 30 v i d drain current (continuos) at t c = 25c 3.2 a i d drain current (continuos) at t c = 100c 2a i dm ( l ) drain current (pulsed) 12.8 a p tot total dissipation at t c = 25c 60 w derating factor 0.48 w/c dv/dt(1) peak diode recovery voltage slope 3.5 v/ns t stg storage temperature C65 to 150 c t j max. operating junction temperature 150 c 3 2 1 1 3 dpak ipak internal schematic diagram
STD3NC50 / STD3NC50-1 2/9 thermal data avalanche characteristics electrical characteristics (tcase = 25 c unless otherwise specified) off on (1) dynamic rthj-case thermal resistance junction-case max 2 c/w rthj-amb thermal resistance junction-ambient max 100 c/w t l maximum lead temperature for soldering purpose 275 c symbol parameter max value unit i ar avalanche current, repetitive or not-repetitive (pulse width limited by t j max) 3.2 a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 210 mj symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 500 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating 1a v ds = max rating, t c = 125 c 50 a i gss gate-body leakage current (v ds = 0) v gs = 30v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs , i d = 250a 234v r ds(on) static drain-source on resistance v gs = 10v, i d = 1.5 a 2.2 2.7 w symbol parameter test conditions min. typ. max. unit g fs (1) forward transconductance v ds > i d(on) x r ds(on)max, i d = 1.5 a 2.7 s c iss input capacitance v ds = 25v, f = 1 mhz, v gs = 0 315 pf c oss output capacitance 52 pf c rss reverse transfer capacitance 7.7 pf
3/9 STD3NC50 / STD3NC50-1 electrical characteristics (continued) switching on switching off source drain diode note: 1. pulsed: pulse duration = 300 s, duty cycle 1.5 %. 2. pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time v dd = 250v, i d = 1.5 a r g = 4.7 w v gs = 10v (see test circuit, figure 3) 10 ns t r rise time 13 ns q g total gate charge v dd = 400v, i d = 3.5 a, v gs = 10v 12.5 17 nc q gs gate-source charge 2.7 nc q gd gate-drain charge 6.1 nc symbol parameter test conditions min. typ. max. unit t r(voff) off-voltage rise time v dd = 400v, i d = 3.5 a, r g = 4.7 w, v gs = 10v (see test circuit, figure 5) 15 ns t f fall time 13 ns t c cross-over time 20 ns symbol parameter test conditions min. typ. max. unit i sd source-drain current 3.2 a i sdm (2) source-drain current (pulsed) 12.8 a v sd (1) forward on voltage i sd = 3.5 a, v gs = 0 1.6 v t rr reverse recovery time i sd = 3.5 a, di/dt = 100a/s, v dd = 100v, t j = 150c (see test circuit, figure 5) 400 ns q rr reverse recovery charge 1.64 c i rrm reverse recovery current 8.2 a safe operating area thermal impedance
STD3NC50 / STD3NC50-1 4/9 capacitance variations output characteristics tranconductance gate charge vs gate-source voltage tranfer characteristics static drain-source on resistance
5/9 STD3NC50 / STD3NC50-1 normalized on resistance vs temperature normalized gate thereshold voltage vs temp. source-drain diode forward characteristics
STD3NC50 / STD3NC50-1 6/9 fig. 5: test circuit for inductive load switching and diode recovery times fig. 4: gate charge test circuit fig. 2: unclamped inductive waveform fig. 1: unclamped inductive load test circuit fig. 3: switching times test circuits for resistive load
7/9 STD3NC50 / STD3NC50-1 dim. mm inch min. typ. max. min. typ. max. a 2.2 2.4 0.086 0.094 a1 0.9 1.1 0.035 0.043 a3 0.7 1.3 0.027 0.051 b 0.64 0.9 0.025 0.031 b2 5.2 5.4 0.204 0.212 b3 0.85 0.033 b5 0.3 0.012 b6 0.95 0.037 c 0.45 0.6 0.017 0.023 c2 0.48 0.6 0.019 0.023 d 6 6.2 0.236 0.244 e 6.4 6.6 0.252 0.260 g 4.4 4.6 0.173 0.181 h 15.9 16.3 0.626 0.641 l 9 9.4 0.354 0.370 l1 0.8 1.2 0.031 0.047 l2 0.8 1 0.031 0.039 a c2 c a3 h a1 d l l2 l1 1 3 = = b3 b b6 b2 e g = = = = b5 2 to-251 (ipak) mechanical data 0068771-e
STD3NC50 / STD3NC50-1 8/9 dim. mm inch min. typ. max. min. typ. max. a 2.20 2.40 0.087 0.094 a1 0.90 1.10 0.035 0.043 a2 0.03 0.23 0.001 0.009 b 0.64 0.90 0.025 0.035 b2 5.20 5.40 0.204 0.213 c 0.45 0.60 0.018 0.024 c2 0.48 0.60 0.019 0.024 d 6.00 6.20 0.236 0.244 e 6.40 6.60 0.252 0.260 g 4.40 4.60 0.173 0.181 h 9.35 10.10 0.368 0.398 l2 0.8 0.031 l4 0.60 1.00 0.024 0.039 v2 0 o 8 o 0 o 0 o p032p_b to-252 (dpak) mechanical data
9/9 STD3NC50 / STD3NC50-1 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no res ponsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devi ces or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com
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